Step 1 : Introduction:

This "How To" addresses a design for a Christmas light controller that runs off a parallel port in the EPP 1.9 mode. This mode offers several advantages over past designs, such as ease of implimentation, superior speed, and reduced programming overhead. Additionally, it is designed to use commpn PC hardware for power supply and inter-module busing, allowing for a much easier build using more readily available parts.

Step 2 : EPP 1.9 Mode?

EPP mode is an update to the parallel port specifications that allows for faster data transfers thru the port than the older SPP or Bi-Directional modes. This is accomplished by adding a controller to the parallel port that automatically sequences all the operations necessary to transfer data in 1 I/O opreational cycle. Also, additional registers were added to the base port address to accomplish this. The EPP port only uses 4 basic instructions which are: Data Write, Data Read, Address Write, and Address Read. These instructions are executed by the user program reading or writing to the appropriate port EPP register address locations (typically port Base Address +3 and Base Address +4).
EPP specs defined 2 flavors, 1.7 and 1.9 with the main defference between them is that under 1.9 rules, the port will wait for the last operation to complete before starting the next operation. EPP 1.7 does not do this, so there could be a potential problem with instruction overlap.
If you want to know more about the various Parallel Port modes of operation, go to http://www.beyondlogic.org and check the section titled "Legacy" for detailed descriptions.

Step 3 : Just how fast is it?

FAST! On my system (P-3 1.5Ghz) running Windows 98SE, I am able to access any one of the end registers at a rate in excess of 130K /per/sec. A P-4 1.8Ghz system I tested ran 160K, so I guess the faster the system, the faster the access up to the max port speed. The variability in the access speed seems to be dependant on the speed of the system to which the parallel port is connected and the programs running in the background. I have not been able to pin down an exact figure on the speed capabilities of a parallel port in EPP mode, but have gathered that it ranges from 2 to 10 Mega-bits per second. My prototype test system runs in the 4 MBS range, so I know I am not accessing it to its full potential. The speed limit is not in the port, but the PC system and Operating System.

Step 4 : Controller front end


The controller consists of 3 basic parts. EPP function Decoder (74LS138), Address/Data storage registers (2 - 74LS573), and a 2-stage address register selection decoder (74LS138 & 74LS154). This is all coupled to a 40 pin IDE (hard disk drive) ribbon cable header to daisy chain to the output register cards.

Step 5 : Output register(s) back end


The output register back end section consists of an 8x8 array of registers (74LS573), and bus buffer chips (2- 74LS245), 2 - 8 position DIP switches for board selection, along with misc inverters (2 - 74LS04) for register latch enable functions. Input to the card is from a daisy chain 40 pin IDE ribbon cable header. Output to the end circuit is via 10 pin IDE ribbon headers. A maximum of 16 Output cards can be chained together to get 16x8x8 or 1024 ports of control. The register chips will directly drive the ULN2803 relay driver chip described in another "How To" on this site. It should also be able to drive the SSRs detailed on this site, but may require addition of a 4.7K pull up resistor to the register output pins, depending on the SSR design.